A curated paper list of existing Artificial Intelligence (AI) for
Electronic Design Automation (EDA) studies.
The list is under construction.
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| 1. |
Enhancing ASIC HLS Design Optimization via Knowledge Transfer from FPGA HLS Models [paper] Su Zheng, Zijian Ding, Chengyue Wang, Bei Yu, Martin Wong, Yizhou Sun, and Jason Cong TCAD 2026 |
| 2. |
Hierarchical mixture of experts: Generalizable learning for high-level synthesis [paper] Weikai Li, Ding Wang, Zijian Ding, Atefeh Sohrabizadeh, Zongyue Qin, Jason Cong, and Yizhou Sun AAAI 2025 |
| 3. |
Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs [paper] Mingzhe Gao, Jieru Zhao, Zhe Lin, and Minyi Guo DATE 2024 |
| 4. |
Cross-modality program representation learning for electronic design automation with high-level synthesis [paper] Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, and Jason Cong MLCAD 2024 |
| 5. |
Robust GNN-based representation learning for HLS [paper] Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong ICCAD 2023 |
| 6. |
Automated accelerator optimization aided by graph neural networks [paper] Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, and Jason Cong DAC 2022 |
| 7. |
High-level synthesis performance prediction using gnns: Benchmarking, modeling, and advancing [paper] Nan Wu, Hang Yang, Yuan Xie, Pan Li, and Cong Hao DAC 2022 |
| 8. |
Correlated Multi-Objective Multi-Fidelity Optimization for HLS Directives Design [paper] Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, and Bei Yu TODAES 2022 |
| 9. |
On learning-based methods for design-space exploration with high-level synthesis [paper] Hung-Yi Liu and Luca P Carloni DAC 2013 |
| 1. |
High-level synthesis directives design optimization via large language model [paper] Xufeng Yao, Wenqian Zhao, Qi Sun, Cheng Zhuo, and Bei Yu TODAES 2025 |
| 1. |
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration [paper] Peng Xu, Su Zheng, Mingzi Wang, Ziyang Yu, Shixin Chen, Tinghuan Chen, Keren Zhu, Tsung-Yi Ho, and Bei Yu TODAES 2025 |
| 2. |
LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration [paper] Donger Luo, Tianyi Li, Xinheng Li, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, and Hao Geng ICCAD 2025 |
| 3. |
Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning [paper] Mingjun Cheng, Shihan Zhang, Xin Zheng, Xian Lin, Huaien Gao, Shuting Cai, Xiaoming Xiong, and Bei Yu TVLSI 2025 |
| 4. |
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework [paper] Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, and Martin DF Wong ICCAD 2021 |
| 5. |
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation [paper] Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, and Zhiru Zhang FPGA 2017 |
| 1. |
Machine Learning for Microarchitecture Power Modeling and Design Space Exploration: A Survey [paper] Jianwang Zhai, Zichao Ling, Chen Bai, Kang Zhao, and Bei Yu J-CRAD 2024 |
| 2. |
APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors [paper] Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, and Shidhartha Das MICRO 2021 |
| 1. |
CHOP: Clustered Hybrid Optimization for Logic Synthesis with Self-Supervised Prediction [paper] Rongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu, Junying Huang, Bei Yu, Qiang Xu, and Tsung-Yi Ho TCAD 2026 |
| 2. |
DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks [paper] Rongliang Fu, Libo Shen, Ziyi Wang, Zhengxing Lei, Zixiao Wang, Junying Huang, Bei Yu, and Tsung-Yi Ho ASP-DAC 2026 |
| 3. |
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning [paper] Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, and Bei Yu ISPD 2025 |
| 1. |
AIG2PT: A Generative Pre-trained Transformer for Unconditional And-Inverter Graph Synthesis [paper] Marcel Walter IWLS 2026 |
| 2. |
Efficient Continuous Logic Optimization with Diffusion Model [paper] [code] Yikang Ouyang, Xiaofei Yu, Jiadong Zhu, Tinghuan Chen, and Yuzhe Ma DAC 2025 |
| 3. |
Circuit Transformer: A Transformer That Preserves Logical Equivalence [paper] [code] Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, and Jun Wang ICLR 2025 |
| 4. |
Logic Synthesis with Generative Deep Neural Networks [paper] Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, and Jun Wang IWLS 2024 |
| 5. |
CircuitSynth: Leveraging Large Language Models for Circuit Topology Synthesis [paper] Prashanth Vijayaraghavan, Luyao Shi, Ehsan Degan, and Xin Zhang LAD 2024 |
| 1. |
iRw: An Intelligent Rewriting [paper] Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, and Bei Yu DATE 2025 |
| 1. |
Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search [paper] Yuyang Ye, Xiangfei Hu, Yuchen Liu, Peng Xu, Yu Gong, Tinghuan Chen, Hao Yan, Bei Yu, and Longxing Shi DAC 2025 |
| 2. |
Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer [paper] Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, and Bei Yu DATE 2025 |
| 3. |
Timing-driven Technology Mapping Approximation Based on Reinforcement Learning [paper] Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, and Longxing Shi TCAD 2024 |
| 1. |
SynAct: A Reasoning-Acting Large Language Model Agent for Adaptive Synthesis Optimization [paper] Fangzhou Liu, Peiyi Han, Jiawei Liu, Yuan Pu, Zhuolun He, Rongliang Fu, Tsung-Yi Ho, and Bei Yu arXiv 2026 |
| 2. |
CB-EVO: Contextual Bandit Tuning with Evolutionary Search for Logic Synthesis [paper] Fangzhou Liu, Wuqian Tang, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Mengjia Dai, Tinghuan Chen, and Bei Yu TODAES 2025 |
| 3. |
PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis [paper] Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, and Kang Zhao ASP-DAC 2025 |
| 4. |
CBTune: Contextual Bandit Tuning for Logic Synthesis [paper] Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen, and Bei Yu DATE 2024 |
| 5. |
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search [paper] Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, and Bei Yu ICCAD 2023 |
| 6. |
Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic Synthesis [paper] Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, Mingxuan Yuan, and Jianye Hao ICCAD 2022 |
| 7. |
Practical Multi-armed Bandits in Boolean Optimization [paper] [code] [talk] Cunxi Yu ICCAD 2020 |
| 8. |
DRiLLS: Deep Reinforcement Learning for Logic Synthesis [paper] [code] Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, and Sherief Reda ASP-DAC 2020 |
| 9. |
Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network [paper] Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, and David Z. Pan MLCAD 2020 |
| 10. |
Developing synthesis flows without human knowledge [paper] [code] [slides] Cunxi Yu, Houping Xiao, and Giovanni De Micheli DAC 2018 |
| 1. |
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization [paper] Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, and Mahdi Biparva ASP-DAC 2025 |
| 2. |
LSTP: A Logic Synthesis Timing Predictor [paper] Haisheng Zheng, Zhuolun He, Fangzhou Liu, Zehua Pei, and Bei Yu ASP-DAC 2024 |
| 3. |
SNS's Not a Synthesizer: A Deep-Learning-Based Synthesis Predictor [paper] [code] Ceyu Xu, Chris Kjellqvist, and Lisa Wu Wills ISCA 2022 |
| 4. |
Bulls-Eye: Active Few-shot Learning Guided Logic Synthesis [paper] Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey, Tushit Jain, Ramesh Karri, and Siddharth Garg TCAD 2022 |
| 5. |
Decision making in synthesis cross technologies using LSTMs and transfer learning [paper] [talk] Cunxi Yu and Wang Zhou MLCAD 2020 |
| 1. |
LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration [paper] Shan Huang, Jinhao Li, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, and Guohao Dai ASP-DAC 2025 |
| 1. |
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment [paper] Wenji Fang, Jing Wang, Yao Lu, Shang Liu, and Zhiyao Xie ICCAD 2025 |
| 2. |
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits [paper] Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Yu Huang, and Bei Yu TCAD 2025 |
| 3. |
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction [paper] Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, and Chuan Shi DATE 2025 |
| 4. |
MOSS: Multi-Modal Representation Learning on Sequential Circuits [paper] Mingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye, Bei Yu, Xiaowei Li, and Huawei Li DAC 2025 |
| 5. |
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment [paper] Haoyuan Wu, Haisheng Zheng, Yuan Pu, and Bei Yu ICLR 2025 |
| 6. |
Polargate: Breaking the functionality representation bottleneck of and-inverter graph neural network [paper] Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, and Chuan Shi ICCAD 2024 |
| 7. |
Functionality matters in netlist representation learning [paper] Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang DAC 2022 |
| 8. |
Graph Learning-Based Arithmetic Block Identification [paper] Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, and Bei Yu ICCAD 2021 |
| 1. |
PrefixLLM: LLM-aided Prefix Circuit Design [paper] Weihua Xiao, Venkata Sai Charan Putrevu, Raghu Vamshi Hemadri, Siddharth Garg, and Ramesh Karri arXiv 2024 |
| 2. |
Machine-Learning-Driven Architectural Selection of Adders and Multipliers in Logic Synthesis [paper] Jiawen Cheng, Yong Xiao, Yun Shao, Guanghai Dong, Songlin Lyu, and Wenjian Yu TODAES 2023 |
| 1. |
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs [paper] Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, and Hongce Zhang ASP-DAC 2025 |
| 2. |
HARM: A Hint-Based Assertion Miner [paper] Samuele Germiniani and Graziano Pravadelli TCAD 2022 |
| 3. |
Hybrid Rule-Based and Machine Learning System for Assertion Generation from Natural Language Specifications [paper] Fnu Aditi and Michael S. Hsiao ATS 2022 |
| 4. |
AutoSVA: Democratizing Formal Verification of RTL Module Interactions [paper] Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, and Margaret Martonosi DAC 2021 |
| 1. |
LLM-Assisted Circuit Verification: A Comprehensive Survey [paper] Hongduo Liu, Yuntao Lu, Mingjun Wang, Xufeng Yao, and Bei Yu ASP-DAC 2026 |
| 2. |
Large Language Models for EDA: Future or Mirage? [paper] Zhuolun He, Yuan Pu, Haoyuan Wu, Tairu Qiu, and Bei Yu TODAES 2025 |
| 3. |
Large Language Models for EDA: From Assistants to Agents [paper] Zhuolun He, Yuan Pu, Haoyuan Wu, Yuhan Qin, Tairu Qiu, and Bei Yu FnT EDA 2025 |
| 4. |
Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect [paper] Nan Wu, Yingjie Li, Hang Yang, Hanqiu Chen, Steve Dai, Cong Hao, Cunxi Yu, and Yuan Xie TODAES 2024 |
| 1. |
A Novel SystemVerilog Assertion Dataset [paper] Anand Menon, Samit Miftah, Shamik Kundu, Souvik Kundu, Amisha Srivastava, Arnab Raha, Gaberiel Sonnenschien, Suvadeep Banerjee, Deepak Mathaikutty, and Kanad Basu TODAES 2025 |
| 1. |
Deep H-GCN: Fast analog IC aging-induced degradation estimation [paper] Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, and Bei Yu TCAD 2021 |
| 2. |
Analog IC aging-induced degradation estimation via heterogeneous graph convolutional networks [paper] Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, and Bei Yu ASP-DAC 2021 |
| 3. |
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network [paper] Seyed Milad Ebrahimipour, Behnam Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, and Lesley Shannon ICCAD 2020 |
| 1. |
Adaptive Stepping PTA for DC Analysis Based on Reinforcement Learning [paper] Yichao Dong, Dan Niu, Zhou Jin, Chuan Zhang, Qi Li, and Changyin Sun TCAS-II 2023 |
| 2. |
OSSP-PTA: An Online Stochastic Stepping Policy for PTA on Reinforcement Learning [paper] Dan Niu, Yichao Dong, Zhou Jin, Chuan Zhang, Qi Li, and Changyin Sun TCAD 2023 |
| 3. |
Accelerating Sparse LU Factorization with Density-aware Adaptive Matrix Multiplication for Circuit Simulation [paper] Tengcheng Wang, Wenhao Li, Haojie Pei, Yuying Sun, Zhou Jin, and Weifeng Liu DAC 2023 |
| 4. |
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation [paper] Wei W. Xing, Xiang Jin, Tian Feng, Dan Niu, Weisheng Zhao, and Zhou Jin TODAES 2022 |
| 5. |
Accelerating Nonlinear DC Circuit Simulation with Reinforcement Learning [paper] Zhou Jin, Haojie Pei, Yichao Dong, Xiang Jin, Xiao Wu, Wei W. Xing, and Dan Niu DAC 2022 |
| 6. |
Application of Deep Learning in Back-End Simulation: Challenges and Opportunities [paper] Yufei Chen, Haojie Pei, Xiao Dong, Zhou Jin, and Cheng Zhuo ASP-DAC 2022 |
| 7. |
Machine-Learning-Driven Matrix Ordering for Power Grid Analysis [paper] Ganqu Cui, Wenjian Yu, Xin Li, Zhiyu Zeng, and Ben Gu DATE 2019 |
| 8. |
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network [paper] Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, and Xuan Zeng ICCAD 2019 |
| 1. |
ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning [paper] Jiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, P. T. Lee, J. H. Yang, H. L. Huang, Y. J. Su, and Charles H.-P. Wen ASP-DAC 2025 |
| 2. |
Deep Learning Inspired Capacitance Extraction Techniques [paper] Wenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, and Chunyan Pei ASP-DAC 2025 |
| 3. |
Few-Shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction [paper] Shan Shen, Yibin Zhang, Hector Rodriguez, and Wenjian Yu DAC 2025 |
| 4. |
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network [paper] Lihao Liu, Fan Yang, Li Shang, and Xuan Zeng TCAD 2024 |
| 5. |
Training Better CNN Models for 3-D Capacitance Extraction with Neural Architecture Search [paper] Haoyuan Li, Dingcheng Yang, and Wenjian Yu DATE 2024 |
| 6. |
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs [paper] Shan Shen, Dingcheng Yang, Yuyang Xie, Chunyan Pei, Wenjian Yu, and Bei Yu GLSVLSI 2024 |
| 7. |
CNN-Cap: Effective Convolutional Neural Network-Based Capacitance Models for Interconnect Capacitance Extraction [paper] Dingcheng Yang, Haoyuan Li, Wenjian Yu, Yuanbo Guo, and Wenjie Liang TODAES 2023 |
| 8. |
CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction [paper] Dingcheng Yang, Wenjian Yu, Yuanbo Guo, and Wenjie Liang ICCAD 2021 |
| 1. |
AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization Shuo Ren, Zijin Cheng, Yaohui Han, Libo Shen, Leilei Jin, Wanting Tian, Rongliang Fu, Chao Wang, Bei Yu, and Tsung-Yi Ho ASP-DAC 2027 |
| 2. |
VeriGRAG: Enhancing LLM-Based Verilog Code Generation with Structure-Aware Soft Prompts Jiayu Zhao, Zehua Pei, Zetao Guo, Bei Yu, and Song Chen ASP-DAC 2027 |
| 3. |
Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective [paper] Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, and Bei Yu ISPD 2026 |
| 4. |
CPPL: A Circuit Prompt Programming Language [paper] Shuo Yin, Yihe Wang, Lancheng Zou, Xufeng Yao, Tinghuan Chen, Chen Bai, Zhengrong Wang, Tsung-Yi Ho, and Bei Yu ICCD 2026 |
| 5. |
LEGO 2.0: A Unified Agentic Platform for Digital Chip Design and Optimization Jincheng Lou, Ruohan Xu, Jiecheng Ma, Boyang Wu, Yuhao Ji, Chunyuan Zhao, Xinyu Qu, Yuxiang Zhao, Runzhe Tao, Bei Yu, Zhixiong Di, and Yibo Lin ICCAD 2026 |
| 6. |
MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA [paper] Zhenghao Chen, Yuan Pu, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu, and Kang Zhao DATE 2026 |
| 7. |
A Multi-Granularity Retrieval Augmented Generation Framework for EDA Tasks Leveraging Knowledge Graph Yuheng Huang, Yuhan Qin, Yuan Pu, Zhaotan Lin, Yuntao Nie, Zhuolun He, Jianwang Zhai, Kang Zhao, and Bei Yu ICCAD 2026 |
| 8. |
Smart-PCLib: A LLM-based Multi-Agent Framework for Automated PCB Component Library Generation [paper] Zhaohai Di, Jindong Tu, Zhiyuan HE, Yuan Pu, Jiawei Liu, Chong Tong, Tsung-Yi Ho, Bei Yu, and Tinghuan Chen DATE 2026 |
| 9. |
Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation [paper] Haoyuan Wu, Haisheng Zheng, Zhuolun He, and Bei Yu NAACL 2025 |
| 10. |
ChatEDA: A Large Language Model Powered Autonomous Agent for EDA [paper] Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, and Bei Yu TCAD 2024 |
| 1. |
Floorplanning with Graph Attention [paper] Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang DAC 2022 |
| 2. |
GraphPlanner: Floorplanning with Graph Neural Network [paper] Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang TODAES 2022 |
| 1. |
MdpoPlanner: Mask-Driven Floorplan via Reinforcement Learning-Based Placement Order [paper] Yue Wu, Caiyu Chen, and Xiaoyan Yang ASP-DAC 2026 |
| 2. |
CORE: Collaborative Optimization with Reinforcement Learning and Evolutionary Algorithm for Floorplanning [paper] [code] Pengyi Li, Shixiong Kai, Jianye Hao, Ruizhe Zhong, Hongyao Tang, Zhentao Tang, Mingxuan Yuan, and Junchi Yan NeurIPS 2025 |
| 3. |
Learning to Floorplan like Human Experts via Reinforcement Learning [paper] Binjie Yan, Lin Xu, Zefang Yu, Mingye Xie, Wei Ran, Jingsheng Gao, Yuzhuo Fu, and Ting Liu DATE 2024 |
| 4. |
Floorplanning with Edge-Aware Graph Attention Network and Hindsight Experience Replay [paper] Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, and Yi Kang TODAES 2024 |
| 1. |
Finetune Chiplet Design Floorplan via KuanNet [paper] Xiaomeng Wang, Zhen Zhou, and Yang Yi TVLSI 2026 |
| 2. |
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration [paper] Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, and Alberto L. Sangiovanni-Vincentelli TCAD 2024 |
| 3. |
RLPlanner: Reinforcement Learning Based Floorplanning for Chiplets with Fast Thermal Analysis [paper] Yuanyuan Duan, Xingchen Liu, Zhiping Yu, Hanming Wu, Leilai Shao, and Xiaolei Zhu DATE 2024 |
| 4. |
Addressing Large Action Spaces in 3D Floorplanning via Spatial Generalization [paper] Fin Amin, Nirjhor Rouf, Tse-Han Pan, Sounak Dutta, Md Kamal Ibn Shafi, and Paul D. Franzon arXiv 2024 |
| 1. |
Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning [paper] Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, and Husni Habal DATE 2025 |
| 2. |
Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search [paper] Sandro Junior Della Rovere, Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, and Husni Habal SMACD 2025 |
| 1. |
Learning-Augmented Multilevel Hypergraph Partitioning with Net-Level Cut Priors Pengju Zhang, Ziyi Wang, Bei Yu, and Zhiang Wang ASP-DAC 2027 |
| 2. |
SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement [paper] Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, and Zhiang Wang ICCAD 2022 |
| 3. |
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs [paper] Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim DAC 2020 |
| 1. |
FloorSet - a VLSI Floorplanning Dataset with Design Constraints of Real-World SoCs [paper] [code] Uday Mallappa, Hesham Mostafa, Mikhail Galkin, Mariano Phielipp, and Somdeb Majumdar ICCAD 2024 |
| 1. |
C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization [paper] Yi-Chen Lu, Hao-Hsiang Hsiao, Rongjian Liang, Wen-Hao Liu, and Haoxing Ren ASP-DAC 2026 |
| 2. |
EvoPlace: Evolution of Optimization Algorithms for Global Placement via Large Language Models [paper] Xufeng Yao, Jiaxi Jiang, Yuxuan Zhao, Peiyu Liao, Yibo Lin, and Bei Yu TCAD 2026 |
| 3. |
Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global Placement [paper] Wenchao Li, Hongxi Wu, Duanxiang Liu, Xingquan Li, and Wenxing Zhu DAC 2025 |
| 4. |
ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator [paper] Xinfei Liu, Siting Liu, Bei Yu, Song Chen, and Qi Xu ASP-DAC 2025 |
| 5. |
Hybrid Modeling and Weighting for Timing-driven Placement with Efficient Calibration [paper] Bangqi Fu, Lixin Liu, Martin D. F. Wong, and Evangeline F. Y. Young ICCAD 2024 |
| 6. |
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning [paper] Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim ISPD 2023 |
| 7. |
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement [paper] Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, and Bei Yu TCAD 2023 |
| 8. |
Global placement with deep learning-enabled explicit routability optimization [paper] Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, and Bei Yu DATE 2021 |
| 9. |
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement [paper] Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, and David Z. Pan DAC 2019 |
| 1. |
Expertise Can Be Helpful for Reinforcement Learning-based Macro Placement [paper] [code] Chengrui Gao, Yunqi Shi, Ke Xue, Ruo-Tong Chen, Siyuan Xu, Mingxuan Yuan, Chao Qian, and Zhi-Hua Zhou ICLR 2026 |
| 2. |
Chip Placement with Diffusion Models [paper] Vint Lee, Minh Nguyen, Leena Elzeiny, Chun Deng, Pieter Abbeel, and John Wawrzynek ICML 2025 |
| 3. |
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy [paper] Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, and Yibo Lin ASP-DAC 2023 |
| 4. |
ChiPFormer: Transferable Chip Placement via Offline Decision Transformer [paper] Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, and Ping Luo ICML 2023 |
| 5. |
AutoDMP: Automated DREAMPlace-based Macro Placement [paper] [code] Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, and Haoxing Ren ISPD 2023 |
| 6. |
Macro Placement by Wire-Mask-Guided Black-Box Optimization [paper] Yunqi Shi, Ke Xue, Song Lei, and Chao Qian NeurIPS 2023 |
| 7. |
The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design [paper] Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye HAO, and Junchi Yan NeurIPS 2022 |
| 8. |
MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning [paper] Yao Lai, Yao Mu, and Ping Luo NeurIPS 2022 |
| 9. |
On Joint Learning for Solving Placement and Routing in Chip Design [paper] Ruoyu Cheng and Junchi Yan NeurIPS 2021 |
| 1. |
Thermal-Aware Chiplet Placement Integrating Evolutionary Reinforcement Learning and Monte Carlo Tree Search Debin Cao, Kanglin Tian, Ze Hao, Yi Huang, Bei Yu, Jianwang Zhai, and Kang Zhao ASP-DAC 2027 |
| 2. |
P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture [paper] Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, and Shouyi Yin ICCAD 2025 |
| 1. |
Mitigating Distribution Shift for Congestion Optimization in Global Placement [paper] Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, and Martin Wong DAC 2023 |
| 2. |
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction [paper] Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, and Martin Wong ICCAD 2023 |
| 3. |
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction [paper] Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, and Pheng Ann Heng DAC 2022 |
| 4. |
Towards Collaborative Intelligence: Routability Estimation Based on Decentralized Private Data [paper] Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, and Yiran Chen DAC 2022 |
| 5. |
Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction [paper] Amur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, and Mark Coates ICCAD 2021 |
| 6. |
Automatic Routability Predictor Development Using Neural Architecture Search [paper] Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chun-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, and Yiran Chen ICCAD 2021 |
| 7. |
High-Definition Routing Congestion Prediction for Large-Scale FPGAs [paper] Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, and David Z. Pan ASP-DAC 2020 |
| 8. |
Painting on placement: Forecasting routing congestion using conditional generative adversarial nets [paper] Cunxi Yu and Zhiru Zhang DAC 2019 |
| 9. |
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis [paper] Jieru Zhao, Tingyuan Liang, Sharad Sinha, and Wei Zhang DATE 2019 |
| 10. |
RouteNet: Routability prediction for mixed-size designs using convolutional neural network [paper] Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, and Jiang Hu ICCAD 2018 |
| 1. |
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning [paper] Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J. -H. Huang, and Evangeline F. Y. Young TCAD 2022 |
| 2. |
PROS: A Plug-in for Routability Optimization Applied in the State-of-the-art Commercial EDA Tool Using Deep Learning [paper] Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, and Evangeline F.Y. Young ICCAD 2020 |
| 3. |
Routability Optimization for industrial Designs at Sub-14nm Process Nodes Using Machine Learning [paper] Wei-Ting J. Chan, Pei-Hsin Ho, Andrew B. Kahng, and Prashant Saxena ISPD 2017 |
| 1. |
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net [paper] Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, and Taewhan Kim ICCAD 2022 |
| 2. |
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions [paper] Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, and Gi-Joon Nam ICCAD 2022 |
| 3. |
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network [paper] Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi Reddy, Shyam Ramji, Gi-Joon Nam, and Jiang Hu ISPD 2020 |
| 4. |
Pin accessibility prediction and optimization with deep learning-based pin pattern recognition [paper] Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, and Henry Sheng DAC 2019 |
| 1. |
ModuPlace: LLM-Assisted Modular PCB Placement via Preference-Optimized Constraint Graph Generation [paper] Yaohui Han, Beichen Li, Mingyang Zhao, Rongliang Fu, Qunsong Ye, Tinghuan Chen, Bei Yu, and Tsung-Yi Ho DAC 2026 |
| 2. |
PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement [paper] Lin Chen, Ran Chen, Shoubo Hu, Xufeng Yao, Zhentao Tang, Shixiong Kai, Siyuan Xu, Mingxuan Yuan, Jianye Hao, Bei Yu, and Jiang Xu ASP-DAC 2025 |
| 1. |
Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction [paper] Byungho Choi, Yonghwi Kwon, Umar Afzaal, and Youngsoo Shin ISCAS 2023 |
| 2. |
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning [paper] Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim TCAD 2021 |
| 3. |
Designing of an Optimization Technique for the Prediction of CTS Outcomes using Neural Network [paper] Shuchi Nagaria and Sujay Deb iSES 2020 |
| 4. |
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization [paper] Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim ICCAD 2019 |
| 1. |
RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning [paper] Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, and Sung Kyu Lim DAC 2023 |
| 2. |
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop [paper] Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, and Avesta Sasan GLSVLSI 2021 |
| 1. |
CNN-Assisted Low-Power Clock Tree Synthesis for 3D ICs [paper] Chenbo Xi, Jindong Zhou, and Pingqiang Zhou ASP-DAC 2026 |
| 2. |
BufFormer: A Generative ML Framework for Scalable Buffering [paper] Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, and Haoxing Ren ASP-DAC 2023 |
| 1. |
CTS-Bench: Benchmarking Graph Coarsening Trade-offs for GNNs in Clock Tree Synthesis [paper] Barsat Khadka, Kawsher Roxy, and Md Rubel Ahmed MLBench 2026 |
| 1. |
Accelerating Detailed Routing Convergence through Offline Reinforcement Learning [paper] Afsara Khan and Austin Rovinski DATE 2026 |
| 2. |
Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-Up and Reroute in Chip Detailed Routing [paper] Yu-Chan Keng, Yu-Chun Pai, Wen-Hao Liu, Haoxing Ren, Danny Liu, Rongjian Liang, Mark Ho, Anthony Agnesina, and Yih-Lang Li DAC 2025 |
| 3. |
Transformer-based Reinforcement Learning for Net Ordering in Detailed Routing [paper] Zhanwen Zhou, Hankz Hankui Zhuo, Jinghua Zhou, and Wushao Wen IJCAI 2025 |
| 4. |
Reinforcement Learning Guided Detailed Routing for Custom Circuits [paper] Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, and Haoxing Ren ISPD 2023 |
| 5. |
Asynchronous reinforcement learning framework for net order exploration in detailed routing [paper] Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, and Yayi Wei DATE 2021 |
| 6. |
Late breaking results: A neural network that routes ICs [paper] Dmitry Utyamishev and Inna Partin-Vaisband DAC 2020 |
| 1. |
Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest [paper] Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Matt Liberty, Hsin-Tzu Chang, and Haoxing Ren ISPD 2025 |
| 1. |
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing [paper] Zhonghua Zhou, Yuxuan Pan, Guy G. F. Lemieux, and André Ivanov TODAES 2023 |
| 1. |
Differentiable Tier Assignment for Timing and Congestion-Aware Routing in 3D ICs [paper] Yuan-Hsiang Lu, Hao-Hsiang Hsiao, Yi-Chen Lu, Haoxing Ren, and Sung Kyu Lim ASP-DAC 2026 |
| 2. |
DPRoute: Deep Learning Framework for Package Routing [paper] Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, and Po-Yang Chen ASP-DAC 2023 |
| 3. |
TRouter: Thermal-driven PCB Routing via Non-Local Crisscross Attention Networks [paper] Tinghuan Chen, Silu Xiong, Huan He, and Bei Yu TCAD 2023 |
| 1. |
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement [paper] Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, and Martin Wong DAC 2023 |
| 1. |
Distill3D: Cross-Stage Knowledge Distillation for Early-Stage 3D IC Timing Prediction Mingjun Wang, Lancheng Zou, Guanqi Li, Feng Gu, Yuntao Lu, Tianmeng Yang, Boyu Han, Jianan Mu, Huawei Li, Sung Kyu Lim, and Bei Yu ICCAD 2026 |
| 2. |
ML-Based AIG Timing Prediction to Enhance Logic Optimization [paper] Wenjing Jiang, Jin Yan, and Sachin S. Sapatnekar DATE 2025 |
| 3. |
Truly Pre-Routing Timing Prediction via Considering Power Delivery Network [paper] Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang, and Longxing Shi DAC 2025 |
| 4. |
Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model [paper] Fahad Rahman Amik, Yousef Safari, Zhanguang Zhang, and Boris Vaisband ASP-DAC 2025 |
| 5. |
NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times [paper] Ziyi Wang, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, and Bei Yu ICCAD 2025 |
| 6. |
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning [paper] Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, and Bei Yu TCAD 2025 |
| 7. |
Prerouting Timing Prediction Across Different Technology Nodes [paper] Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Jiaxi Jiang, Ziyi Wang, Peng Xu, Hong Xu, and Bei Yu TCAD 2025 |
| 8. |
Bridging Layout and RTL: Knowledge Distillation based Timing Prediction [paper] Mingjun Wang, Yihan Wen, Bin Sun, Jianan Mu, Juan Li, Xiaoyi Wang, Jing Justin Ye, Bei Yu, and Huawei Li ICML 2025 |
| 9. |
Machine-Learning Based Delay Prediction for FPGA Technology Mapping [paper] Hailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, and Ismail Bustany SLIP 2023 |
| 10. |
A timing engine inspired graph neural network model for pre-routing slack prediction [paper] Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z Pan, and Yibo Lin DAC 2022 |
| 11. |
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation [paper] Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, and Yiran Chen ASP-DAC 2021 |
| 12. |
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks [paper] Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, and Zhiru Zhang ICCAD 2020 |
| 13. |
Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism [paper] Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, and Jiang Hu DAC 2019 |
| 14. |
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning [paper] Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin DATE 2019 |
| 1. |
GNN-Based Timing Yield Prediction From Statistical Static Timing Analysis [paper] Chenbo Xi, Liang Zhang, Biwei Xie, and Pingqiang Zhou ASP-DAC 2026 |
| 2. |
GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph Transformer [paper] Lihao Liu, Beisi Lu, Yunhui Li, Li Shang, and Fan Yang DAC 2025 |
| 3. |
Restructure-Tolerant Timing Prediction via Multimodal Fusion [paper] Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, and Bei Yu DAC 2023 |
| 4. |
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis [paper] Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, and Longxing Shi ASP-DAC 2023 |
| 5. |
Fast and Accurate Wire Timing Estimation Based on Graph Learning [paper] Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, and Longxing Shi DATE 2023 |
| 6. |
Leveraging Machine Learning for Gate-Level Timing Estimation Using Current Source Models and Effective Capacitance [paper] Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, and George Stamoulis GLSVLSI 2022 |
| 7. |
Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures [paper] Hsien-Han Cheng, Iris Hui-Ru Jiang, and Oscar Ou DAC 2020 |
| 8. |
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis [paper] Andrew B. Kahng, Uday Mallappa, and Lawrence Saul ICCD 2018 |
| 9. |
A Deep Learning Methodology to Proliferate Golden Signoff Timing [paper] Seung-Soo Han, Andrew B Kahng, Siddhartha Nath, and Ashok S Vydyanathan DATE 2014 |
| 1. |
Crosstalk Timing Prediction via Graph Prompt Learning in Aggressor-Victim RC Networks [paper] Yuren Zhou, Fan Yang, Zihao Zeng, Yifan Wang, Yuyang Ye, and Qing He DAC 2026 |
| 2. |
ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs [paper] Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, and Tsung-Yi Ho ICCAD 2025 |
| 3. |
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays [paper] Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, and Bei Yu ISPD 2025 |
| 4. |
Routing-free crosstalk prediction [paper] Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, and Gi-Joon Nam ICCAD 2020 |
| 5. |
SI for free: machine learning of interconnect coupling delay and transition effects [paper] Andrew B. Kahng, Mulong Luo, and Siddhartha Nath SLIP 2015 |
| 6. |
Learning-based approximation of interconnect delay and slew in signoff timing tools [paper] Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, and Jyoti Wadhwani SLIP 2013 |
| 1. |
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis [paper] Ioannis Tsiokanos, Styliani Tompazi, Giorgis Georgakoudis, Lev Mukhanov, and Georgios Karakonstantis TC 2022 |
| 2. |
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning [paper] Styliani Tompazi, Ioannis Tsiokanos, Jesus Martinez del Rincon, and Georgios Karakonstantis IEEE Design & Test 2021 |
| 3. |
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations [paper] Dongning Ma, Xinqiao Zhang, Ke Huang, Yu Jiang, Wanli Chang, and Xun Jiao TCAD 2021 |
| 4. |
TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations [paper] Xun Jiao, Dongning Ma, Wanli Chang, and Yu Jiang DAC 2020 |
| 5. |
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search [paper] Ioannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, and Georgios Karakonstantis DATE 2020 |
| 6. |
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units [paper] Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, Jose Pineda de Gyvez, and Rajesh K. Gupta TC 2017 |
| 1. |
AI-Driven, Timing-Aware Power Optimization [paper] Amit Sharma arXiv 2026 |
| 2. |
Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area Overhead [paper] Joonyoung Seo, Jonghyeon Nam, Howoo Jang, Yoonseok Jung, and Seokhyeong Kang ICCAD 2025 |
| 3. |
Generative Self-Supervised Learning for Gate Sizing: Invited [paper] Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren DAC 2022 |
| 1. |
MFRLNet: A Layout Hotspot Detection Network Based on Multi-feature Representation Learning [paper] Han Chen, Ziqiang Cao, Zhaori Bi, Jun Tang, Ke Wang, Ming Zhu, and Xiulong Wu TODAES 2026 |
| 2. |
Lithography Hotspot Detection for Complex Non-Manhattan Layouts via Graph Neural Network [paper] Bohao Li, Ranran Liu, Yumeng Liu, Cong Jiang, Kang Liu, Bei Yu, Kun Ren, Qi Sun, and Cheng Zhuo DATE 2026 |
| 3. |
Node2Node: Node Adaptation with Transformer for Cross-Node Hotspot Detection [paper] Wenbo Xu, Silin Chen, Yibo Huang, Xinyun Zhang, Zixiao Wang, Bei Yu, and Ningmu Zou DATE 2026 |
| 4. |
Delving into Topology Representation for Layout Pattern: A Novel Contrastive Learning Framework for Hotspot Detection [paper] Silin Chen, Kangjian Di, Guohao Wang, Wenzheng Zhao, Li Du, and Ningmu Zou DAC 2025 |
| 5. |
LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding [paper] Yuyang Chen, Yiwen Wu, Jingya Wang, Tao Wu, Xuming He, Jingyi Yu, and Hao Geng DAC 2024 |
| 6. |
Hotspot Detection via Attention-Based Deep Layout Metric Learning [paper] Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, and Bei Yu TCAD 2022 |
| 7. |
Efficient Hotspot Detection via Graph Neural Network [paper] Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, and Xuan Zeng DATE 2022 |
| 8. |
Robustify ML-Based Lithography Hotspot Detectors [paper] Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, and Yiran Chen ICCAD 2022 |
| 9. |
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration [paper] Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, and Bei Yu DAC 2021 |
| 10. |
Hotspot Detection via Multi-task Learning and Transformer Encoder [paper] Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, and Martin D.F. Wong ICCAD 2021 |
| 11. |
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble [paper] Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, and Xuan Zeng TCAD 2020 |
| 12. |
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning [paper] Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, and Bei Yu TCAD 2020 |
| 1. |
GEMIR: Graph-Based Joint Modeling of Electromigration and IR Drop for Power Grid [paper] Feng Guo, Yueyue Xi, Jingyu Jia, Jiawei Liu, Tianshu Hou, Yuyang Ye, Jianwang Zhai, Kang Zhao, and Chuan Shi DAC 2026 |
| 2. |
Consolidating ML-driven Early IR-drop Mitigation for Fast and Reliable IR-drop Closure [paper] Munwon Lee, Chanhee Jeon, and Taewhan Kim DATE 2026 |
| 3. |
Disentangled Multimodal Learning for Scalable Dynamic IR-Drop Analysis Yihan Wen, Su Zheng, Tianshu Hou, Shiping Wu, Yuzhou Feng, and Bei Yu NeurIPS 2026 |
| 4. |
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning [paper] Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, and Chuan Shi DATE 2025 |
| 5. |
Peak Power and Dynamic IR-drop Assessment via Waveform Augmenting [paper] Yihan Wen, Juan Li, Bei Yu, and Xiaoyi Wang ICCAD 2024 |
| 6. |
Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR-Drop Reduction [paper] Seungmin Woo, Hyunsoo Lee, Yunjeong Shin, MinSeok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim, and Taigon Song DATE 2024 |
| 7. |
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs [paper] Daijoon Hyun, Younggwang Jung, Insu Cho, and Youngsoo Shin ASP-DAC 2023 |
| 8. |
Vector-Based Dynamic IR-drop Prediction Using Machine Learning [paper] Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chieo-Mo Li, Norman Chang, Ying-Shiun Li, and Wen-Tze Chuang ASP-DAC 2022 |
| 9. |
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification [paper] Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, and Sachin S. Sapatnekar DATE 2021 |
| 10. |
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks [paper] Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, and Sachin S. Sapatnekar ASP-DAC 2021 |
| 11. |
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance [paper] Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, and Cheng-Hong Tsai ICCAD 2020 |
| 12. |
XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network [paper] Chi-Hsien Pao, An-Yu Su, and Yu-Min Lee DATE 2020 |
| 13. |
Fast IR Drop Estimation with Machine Learning [paper] Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, and Yiran Chen ICCAD 2020 |
| 14. |
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network [paper] Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, and Yiran Chen ASP-DAC 2020 |
| 15. |
GridNet: Fast Data-Driven EM-induced IR Drop Prediction and Localized Fixing for on-Chip Power Grid Networks [paper] Han Zhou, Wentian Jin, and Sheldon X.-D. Tan ICCAD 2020 |
| 16. |
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop [paper] Chia-Tung Ho and Andrew B. Kahng ICCAD 2019 |
| 17. |
Machine-Learning-Based Dynamic IR Drop Prediction for ECO [paper] Yen-Chun Fang, Heng-Yi Lin, Min-Yan Sui, Chien-Mo Li, and Eric Jia-Wei Fang ICCAD 2018 |
| 1. |
Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing [paper] Yuyang Ye, Peng Xu, Lizheng Ren, Tinghuan Chen, Hao Yan, Bei Yu, and Longxing Shi TCAD 2025 |
| 2. |
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL [paper] Hongxi Wu, Zhipeng Huang, Xingquan Li, and Wenxing Zhu Integration 2024 |
| 3. |
Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration [paper] Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, and Pheng-Ann Heng ICCAD 2022 |
| 4. |
TransSizer: A Novel Transformer-Based Fast Gate Sizer [paper] Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren ICCAD 2022 |
| 5. |
Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning [paper] Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim DAC 2021 |
| 6. |
GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning [paper] Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, and Song Han DAC 2020 |
| 1. |
ML-Power: Machine Learning based Power Estimation for SoCs [paper] Sujay Pandit, Sujit Dey, and Anand Raghunathan ISLPED 2025 |
| 2. |
Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs [paper] Jincong Lu, Jinwei Zhang, Wentian Jin, Sachin Sachdeva, and Sheldon X. -D. Tan ASP-DAC 2023 |
| 3. |
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning [paper] Jianwang Zhai, Yici Cai, and Bei Yu ASP-DAC 2023 |
| 1. |
Mixed-Type Wafer Failure Pattern Recognition [paper] Hao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, and Bei Yu ASP-DAC 2023 |
| 2. |
Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries [paper] Florian Klemme and Hussam Amrouch TCAS-I 2022 |
| 3. |
Scalable Machine Learning to Estimate the Impact of Aging on Circuits Under Workload Dependency [paper] Florian Klemme and Hussam Amrouch TCAS-I 2022 |
| 4. |
Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization [paper] Florian Klemme and Hussam Amrouch TCAS-I 2021 |
| 1. |
Chain of SRAF Generation: A Large Reasoning Model for Sub-resolution Assist Features Jiale Li, Silin Chen, Yufeng Zhang, Zhili Xu, Yiqing Wang, Wenbo Xu, Ziyang Yu, Bei Yu, and Ningmu Zou ASP-DAC 2027 |
| 2. |
Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning [paper] Ziyang Yu, Shuo Yin, Su Zheng, Xiaoxiao Liang, Yuzhe Ma, and Bei Yu DAC 2026 |
| 3. |
Fast Inverse Lithography via GRPO Reinforced Flow Matching [paper] Yao Lai, Xuyuan Xiong, Zeyue Xue, Guojin Chen, Jing Wang, Xihui Liu, Rui Zhang, Robert D. Mullins, Bei Yu, and Ping Luo ICML 2026 |
| 4. |
INN-ILT: Inverse Lithography Technique via Invertible Neural Network [paper] Binwu Zhu, Siliang Fei, and Bei Yu TCAD 2026 |
| 5. |
Moreau-ILT: Efficient Inverse Lithography Exploiting Weak Convexity Chaofan Wang, Ziyang Yu, Su Zheng, Zixiao Wang, Yifan Shi, and Bei Yu ICCAD 2026 |
| 6. |
NODE-ILT: Learning the Neural Ordinary Differential Equation for Full-Chip Inverse Lithography Techniques Su Zheng, Shuo Yin, Ziyang Yu, Bei Yu, and Martin Wong ICCD 2026 |
| 7. |
Scalable Second-Order Optimizer for Full-Chip Inverse Lithography Techniques [paper] Su Zheng, Ziyang Yu, Bei Yu, and Martin Wong DATE 2026 |
| 8. |
LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language Model [paper] Tianyi Li, Zhexin Tang, Tao Wu, Bei Yu, Jingyi Yu, and Hao Geng DATE 2025 |
| 9. |
Adaptive ILT via Multi-level Lithography Simulation [paper] Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, and Xuan Zeng TCAD 2025 |
| 10. |
RuleLearner: OPC Rule Extraction from Inverse Lithography Technique Engine [paper] Ziyang Yu, Su Zheng, Wenqian Zhao, Shuo Yin, Xiaoxiao Liang, Guojin Chen, Yuzhe Ma, Bei Yu, and Martin D.F. Wong TCAD 2025 |
| 11. |
Efficient Bilevel Source Mask Optimization [paper] Guojin Chen, Hongquan He, Peng Xu, Hao Geng, and Bei Yu DAC 2024 |
| 12. |
EMOGen: Enhancing Mask Optimization via Pattern Generation [paper] Su Zheng, Yuzhe Ma, Bei Yu, and Martin D. F. Wong DAC 2024 |
| 13. |
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning [paper] Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, and Yuzhe Ma DAC 2024 |
| 14. |
L2O-ILT: Learning to Optimize Inverse Lithography Techniques [paper] Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, and Martin Wong TCAD 2024 |
| 15. |
RL-OPC: Mask Optimization with Deep Reinforcement Learning [paper] Xiaoxiao Liang, Yikang Ouyang, Haoyu Yang, Bei Yu, and Yuzhe Ma TCAD 2024 |
| 16. |
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion [paper] Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, and Martin D.F. Wong TCAD 2024 |
| 17. |
Data-Driven Approaches for Process Simulation and Optical Proximity Correction [paper] Hao-Chiang Shao, Chia-Wen Lin, and Shao-Yun Fang ASP-DAC 2023 |
| 18. |
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation [paper] Ziyang Yu, Peiyu Liao, Yuzhe Ma, Bei Yu, and Martin D. F. Wong TCAD 2023 |
| 19. |
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns [paper] Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, and Martin Wong ICCAD 2022 |
| 20. |
DevelSet: Deep Neural Level Set for Instant Mask optimization [paper] Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, and Bei Yu ICCAD 2021 |
| 21. |
DAMO: Deep Agile Mask Optimization for Full Chip Scale [paper] Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, and Bei Yu ICCAD 2020 |
| 22. |
GAN-OPC: Mask Optimization with Lithography-Guided Generative Adversarial Nets [paper] Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, and Evangeline F. Y. Young DAC 2018 |
| 1. |
SGLayout: Schema-Guided Closed-Loop Refinement for LLM-Driven Parameterized Layout Generation Siyang Chen, Yuan Pu, Yuhan Qin, Zhaotan Lin, Siyuan Liang, Zhuolun He, Lining Zhang, and Bei Yu ICCAD 2026 |
| 2. |
Expert-level Leaf Cell Layout Generation via Preference-Optimized LLM [paper] Yaohui Han, Rongliang Fu, Yanming Liu, Shuo Ren, Shuai Dong, Yunpeng Wang, Tinghuan Chen, Bei Yu, and Tsung-Yi Ho ICML 2026 |
| 3. |
LibPilot: Knowledge-Constrained Dual-Agent Reasoning for Standard Cell Library Tuning Yanfang Liu, Zijin Cheng, Mingjun Wang, Rongliang Fu, Chao Wang, and Bei Yu ICCAD 2026 |
| 4. |
DiffPattern: Layout Pattern Generation via Discrete Diffusion [paper] Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, and Bei Yu DAC 2023 |
| 5. |
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling [paper] Liangjian Wen, Yi Zhu, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, and Chunjing Xu ICCAD 2022 |
| 1. |
DiffResist: Physics-Constrained Diffusion for Photoresist Modeling [paper] Zixiao Wang, Jieya Zhou, Xinyun Zhang, Shoubo Hu, Farzan Farnia, and Bei Yu DATE 2026 |
| 2. |
LMLitho: A Large Vision Model-Driven Lithography Simulation Framework [paper] Zhen Wang, Hongquan He, Tao Wu, Xuming He, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, and Hao Geng ICCAD 2025 |
| 3. |
LithoSim: A Large, Holistic Lithography Simulation Benchmark for AI-Driven Semiconductor Manufacturing [paper] Hongquan He, Zhen Wang, Jingya Wang, Tao Wu, Xuming He, Bei Yu, Jingyi Yu, and Hao Geng NeurIPS 2025 |
| 4. |
Streamlining Computational Lithography with Efficient Pattern Database [paper] Su Zheng, Wenqian Zhao, Shuyuan Sun, Fan Yang, Bei Yu, and Martin D.F. Wong TCAD 2025 |
| 5. |
TorchLitho 2.0: Ultrafast Differentiable Lithography Simulation Engine [paper] Shuo Yin, Su Zheng, Ziyang Yu, and Bei Yu ASICON 2025 |
| 6. |
Open-Source Differentiable Lithography Imaging Framework [paper] Guojin Chen, Hao Geng, Bei Yu, and David Z. Pan SPIE 2024 |
| 7. |
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields [paper] Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, and Martin Wong DAC 2023 |
| 8. |
Enabling Scalable AI Computational Lithography with Physics-Inspired Models [paper] Haoyu Yang and Haoxing Ren ASP-DAC 2023 |
| 9. |
LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing [paper] [code] Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, and Martin Wong NeurIPS 2023 |
| 10. |
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography [paper] [code] Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, and Ru Huang ICCAD 2022 |
| 11. |
Generic Lithography Modeling with Dual-Band Optics-Inspired Neural Networks [paper] Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, and Haoxing Ren DAC 2022 |
| 1. |
SACPlace: Multi-Agent Deep Reinforcement Learning for Symmetry-Aware Analog Circuit Placement [paper] Lei Cai, Guojing Ge, Guibo Zhu, Jixin Zhang, Jinqiao Wang, Bowen Jia, and Ning Xu DATE 2025 |
| 2. |
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction [paper] Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, and Yiran Chen ASP-DAC 2023 |
| 3. |
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits [paper] Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, and David Z. Pan ASP-DAC 2022 |
| 4. |
TAG: Learning Circuit Spatial Embedding from Layouts [paper] Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, and Haoxing Ren ICCAD 2022 |
| 5. |
Are Analytical Techniques Worthwhile for Analog IC Placement? [paper] Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, and Jiang Hu DATE 2022 |
| 6. |
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks [paper] Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, and Yibo Lin ASP-DAC 2021 |
| 7. |
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks [paper] Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan DAC 2021 |
| 8. |
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning [paper] Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z. Pan DATE 2020 |
| 9. |
A Customized Graph Neural Network Model for Guiding Analog IC Placement [paper] Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, and Jiang Hu ICCAD 2020 |
| 10. |
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout [paper] Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, and David Z. Pan DAC 2019 |
| 1. |
HyperAnalog: Domain-Aware Hypergraph Transformer for Analog Circuit Representation Learning [paper] Taejin Paik and Suwan Kim DAC 2026 |
| 2. |
KCLNet: Electrically Equivalence-Oriented Graph Representation Learning for Analog Circuits [paper] Peng Xu, Yapeng Li, Tinghuan Chen, Tsung-Yi Ho, and Bei Yu AAAI 2026 |
| 3. |
Ckt2Vec: Efficient Electrical Encoding for Analog Circuit Representations in Vector Space [paper] Peng Xu, Yapeng Li, Tinghuan Chen, Tsung-Yi Ho, and Bei Yu TCAD 2026 |
| 4. |
SMART: Graph Learning-Boosted Subcircuit Matching for Large-scale Analog Circuits [paper] Jindong Tu, Yapeng Li, Pengjia Li, Peng Xu, Qianru Zhang, Sanping Wan, Yongsheng Sun, Bei Yu, and Tinghuan Chen TCAD 2025 |
| 1. |
GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement Learning [paper] Dongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, Inchul Jeong, Joohwan Cho, and Jongsun Park DAC 2025 |
| 2. |
Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing [paper] Mohsen Ahmadzadeh and Georges G. E. Gielen DAC 2024 |
| 3. |
APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning [paper] Ahmet Faruk Budak, David Smart, Brian Swahn, and David Z. Pan ASP-DAC 2023 |
| 4. |
RoSE: Robust Analog Circuit Parameter Optimization with Sampling-Efficient Reinforcement Learning [paper] Jian Gao, Weidong Cao, and Xuan Zhang DAC 2023 |
| 1. |
DaVinci: Performance-Driven Analog Routing via Multimodality Guidance Prediction [paper] Peng Xu, Rong Sun, Su Zheng, Song Chen, Qi Xu, and Bei Yu TCAD 2026 |
| 2. |
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation [paper] Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, and Bei Yu DAC 2024 |
| 3. |
GeniusRoute: A new analog routing paradigm using generative neural network guidance [paper] Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z Pan ICCAD 2019 |
| 1. |
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line [paper] Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, and Ru Huang DAC 2023 |
| 2. |
Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks [paper] Ahmet F. Budak, Keren Zhu, and David Z. Pan ICCAD 2023 |
| 3. |
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis [paper] [code] [slides] Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, and David Z. Pan DAC 2019 |
| 1. |
A Deep Learning Approach for Efficient Electromagnetic Analysis of On-Chip Inductor with Dummy Metal Fillings [paper] Xiangliang Li, Yijie Tang, Peng Zhao, Shichang Chen, Kuiwen Xu, and Gaofeng Wang Electronics 2022 |
| 2. |
Applications of physics-informed neural networks in power systems-a review [paper] Bin Huang and Jianhui Wang Transactions on Power Systems 2022 |
| 1. |
DiffCool: Label-Free Synthesis of Chip-Tailored Heat Sinks via Thermal-Aware Diffusion Siyuan Liang, Zixiao Wang, Chenghan Wang, Shanyi Li, Yushen Zhang, Leilei Jin, Zhen Zhuang, Ulf Schlichtmann, Bei Yu, and Tsung-Yi Ho NeurIPS 2026 |
| 2. |
A Thermal Machine Learning Solver For Chip Simulation [paper] Rishikesh Ranade, Haiyang He, Jay Pathak, Norman Chang, Akhilesh Kumar, and Jimin Wen MLCAD 2022 |
| 3. |
Fast Thermal Analysis for Chiplet Design based on Graph Convolution Networks [paper] Liang Chen, Wentian Jin, and Sheldon X-D Tan ASP-DAC 2022 |
| 1. |
HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural Network [paper] Wentian Jin, Liang Chen, Subed Lamichhane, Mohammadamir Kavousi, and Sheldon X-D Tan ICCAD 2022 |
| 2. |
A Space-Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing [paper] Tianshu Hou, Ngai Wong, Quan Chen, Zhigang Ji, and Hai-Bao Chen TCAD 2022 |
| 1. |
LaMAGIC: Advanced Circuit Formulations for Language-Model-based Topology Generation for Analog Integrated Circuits [paper] Chen-Chia Chang, Wan-Hsuan Lin, Yikang Shen, Guanglei Zhou, Yiran Chen, and Xin Zhang TODAES 2026 |
| 2. |
Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout [paper] Hyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, and David Z. Pan ICCAD 2025 |
| 3. |
AnalogCoder: Analog Circuit Design via Training-Free Code Generation [paper] Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, and Ping Luo AAAI 2025 |
| 4. |
LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation [paper] Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, and David Z. Pan arXiv 2024 |
| 1. |
Explainable GNN-Driven Test Point Insertion on Uncontrollable I/Os [paper] Sung-Hyuk Cho, Tae-Min Park, Jeongyeol Lee, Jae-Youn Hong, Andreas Gerstlauer, and Joon-Sung Yang DATE 2026 |
| 2. |
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning [paper] Shao-Chun Hung, Arjun Chaudhuri, and Krishnendu Chakrabarty ETS 2023 |
| 3. |
DeepTPI: Test Point Insertion with Deep Reinforcement Learning [paper] Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, and Qiang Xu ITC 2022 |
| 1. |
SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning [paper] Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, and Huawei Li DAC 2024 |
| 2. |
FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator [paper] Yuyang Ye, Zonghui Wang, Zun Xue, Ziqi Wang, Yifei Gao, and Hao Yan GLSVLSI 2023 |
| 3. |
Neural Fault Analysis for SAT-based ATPG [paper] Junhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, and Yu Huang ITC 2022 |
| 1. |
High Performance Graph Convolutional Networks with Applications in Testability Analysis [paper] Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, and Bei Yu DAC 2019 |
| 1. |
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs [paper] Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, and Krishnendu Chakrabarty ITC 2023 |
| 1. |
ChatTest: Coverage-Enhanced Testbench Generation for Agile Hardware Verification with LLMs [paper] Gwok-Waa Wan, Shengchu Su, Jingyi Zhang, Sam Zaak Wong, Mengnv Xing, Lei Ji, Zhe Jiang, Xi Wang, and Jun Yang DATE 2026 |
| 2. |
ChatFCM: Comprehension-Synthesis Decoupling for LLM-Based Functional Coverage Model Generation Yuan Pu, Yudong He, Zhenghao Chen, Mingjun Wang, Bingkun Yao, Zhaotan Lin, Qin Chen, Bing Li, Song Chen, Zhuolun He, Wenjian Yu, Yanfeng Li, and Bei Yu ICCAD 2026 |
| 1. |
CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design [paper] Mingjun Wang, Yihan Wen, Yuntao Lu, Fengrui Liu, Yuxiang Zhao, Boyu Han, Jianan Mu, Yibo Lin, Runsheng Wang, Huawei Li, and Bei Yu ICLR 2026 |
| 2. |
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms [paper] Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, and Ru Huang ICCAD 2023 |
| 3. |
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA) [paper] [code] Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, and Ru Huang SCIENCE CHINA Information Sciences 2022 |
| 1. |
RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model [paper] Yao Lu, Shang Liu, Qijun Zhang, and Zhiyao Xie ASP-DAC 2024 |
| 2. |
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation [paper] Shang Liu, Yao Lu, Wenji Fang, Mengming Li, and Zhiyao Xie ICCAD 2024 |
| 3. |
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects [paper] Ahmed Allam and Mohamed Shalan LAD 2024 |
| 4. |
Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation [paper] Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, and Haoxing Ren ICCAD 2023 |
| 1. |
Evaluating Agentic AI for Chip Design: Information Loss in Cost-Deadline Benchmarks [paper] [project] Amit Sharma Zenodo 2026 |
| 2. |
Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA [paper] Yuan Pu, Zhuolun He, Yuqi Jiang, Tairu Qiu, Haoyuan Wu, Qi Sun, Cheng Zhuo, and Bei Yu TCAD 2025 |
cited as
@article{chen2023ai4eda,
title = {Awesome AI for EDA: A curated paper list of Artificial Intelligence for Electronic Design Automation studies.},
author = {Chen, Guojin and Mai, Jing and Lin, Yibo and Yu, Bei},
journal = {ai4eda.github.io},
year = {2023},
url = {https://ai4eda.github.io/}
}
Last updated on 2026-10-27 .