A curated paper list of existing Artificial Intelligence (AI) for
Electronic Design Automation (EDA) studies.
The list is under construction.
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| 1. |
Correlated Multi-Objective Multi-Fidelity Optimization for HLS Directives Design [paper] Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, and Bei Yu TODAES 2022 |
| 2. |
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis [paper] Jieru Zhao, Tingyuan Liang, Sharad Sinha, and Wei Zhang DATE 2019 |
| 3. |
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation [paper] Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, and Zhiru Zhang FPGA 2017 |
| 4. |
On learning-based methods for design-space exploration with high-level synthesis [paper] Hung-Yi Liu and Luca P Carloni DAC 2013 |
| 1. |
AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search [paper] Zehua Pei, Fangzhou Liu, Zhuolun He, Guojin Chen, Haisheng Zheng, Keren Zhu, and Bei Yu ICCAD 2023 |
| 2. |
Practical Multi-armed Bandits in Boolean Optimization [paper] [code] [talk] Cunxi Yu ICCAD 2020 |
| 3. |
DRiLLS: Deep Reinforcement Learning for Logic Synthesis [paper] [code] Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, and Sherief Reda ASP-DAC 2020 |
| 1. |
Machine-Learning-Driven Architectural Selection of Adders and Multipliers in Logic Synthesis [paper] Jiawen Cheng, Yong Xiao, Yun Shao, Guanghai Dong, Songlin Lyu, and Wenjian Yu TODAES 2023 |
| 1. |
SNS's Not a Synthesizer: A Deep-Learning-Based Synthesis Predictor [paper] [code] Ceyu Xu, Chris Kjellqvist, and Lisa Wu Wills ISCA 2022 |
| 2. |
Bulls-Eye: Active Few-shot Learning Guided Logic Synthesis [paper] Animesh Basak Chowdhury, Benjamin Tan, Ryan Carey, Tushit Jain, Ramesh Karri, and Siddharth Garg TCAD 2022 |
| 3. |
Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic Synthesis [paper] Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, Mingxuan Yuan, and Jianye Hao ICCAD 2022 |
| 4. |
Decision making in synthesis cross technologies using LSTMs and transfer learning [paper] [talk] Cunxi Yu and Wang Zhou MLCAD 2020 |
| 5. |
Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network [paper] Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, and David Z. Pan MLCAD 2020 |
| 6. |
Developing synthesis flows without human knowledge [paper] [code] [slides] Cunxi Yu, Houping Xiao, and Giovanni De Micheli DAC 2018 |
| 1. |
Functionality matters in netlist representation learning [paper] Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang DAC 2022 |
| 2. |
Graph Learning-Based Arithmetic Block Identification [paper] Zhuolun He, Ziyi Wang, Chen Bail, Haoyu Yang, and Bei Yu ICCAD 2021 |
| 3. |
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network [paper] Seyed Milad Ebrahimipour, Behnam Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, and Lesley Shannon ICCAD 2020 |
| 4. |
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network [paper] Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, and Xuan Zeng ICCAD 2019 |
| 1. |
Mixed-Type Wafer Failure Pattern Recognition [paper] Hao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, and Bei Yu ASP-DAC 2023 |
| 2. |
Deep H-GCN: Fast analog IC aging-induced degradation estimation [paper] Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, and Bei Yu TCAD 2021 |
| 3. |
Analog IC aging-induced degradation estimation via heterogeneous graph convolutional networks [paper] Tinghuan Chen, Qi Sun, Canhui Zhan, Changze Liu, Huatao Yu, and Bei Yu ASP-DAC 2021 |
| 1. |
Rethink before Releasing Your Model: ML Model Extraction Attack in EDA [paper] Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, and Yiran Chen ASP-DAC 2023 |
| 1. |
CNN-Cap: Effective Convolutional Neural Network-Based Capacitance Models for Interconnect Capacitance Extraction [paper] Dingcheng Yang, Haoyuan Li, Wenjian Yu, Yuanbo Guo, and Wenjie Liang TODAES 2023 |
| 2. |
CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction [paper] Dingcheng Yang, Wenjian Yu, Yuanbo Guo, and Wenjie Liang ICCAD 2021 |
| 1. |
Adaptive Stepping PTA for DC Analysis Based on Reinforcement Learning [paper] Yichao Dong, Dan Niu, Zhou Jin, Chuan Zhang, Qi Li, and Changyin Sun TCAS-II 2023 |
| 2. |
OSSP-PTA: An Online Stochastic Stepping Policy for PTA on Reinforcement Learning [paper] Dan Niu, Yichao Dong, Zhou Jin, Chuan Zhang, Qi Li, and Changyin Sun TCAD 2023 |
| 3. |
Accelerating Sparse LU Factorization with Density-aware Adaptive Matrix Multiplication for Circuit Simulation [paper] Tengcheng Wang, Wenhao Li, Haojie Pei, Yuying Sun, Zhou Jin, and Weifeng Liu DAC 2023 |
| 4. |
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation [paper] Wei W. Xing, Xiang Jin, Tian Feng, Dan Niu, Weisheng Zhao, and Zhou Jin TODAES 2022 |
| 5. |
Accelerating Nonlinear DC Circuit Simulation with Reinforcement Learning [paper] Zhou Jin, Haojie Pei, Yichao Dong, Xiang Jin, Xiao Wu, Wei W. Xing, and Dan Niu DAC 2022 |
| 6. |
Application of Deep Learning in Back-End Simulation: Challenges and Opportunities [paper] Yufei Chen, Haojie Pei, Xiao Dong, Zhou Jin, and Cheng Zhuo ASP-DAC 2022 |
| 7. |
Machine-Learning-Driven Matrix Ordering for Power Grid Analysis [paper] Ganqu Cui, Wenjian Yu, Xin Li, Zhiyu Zeng, and Ben Gu DATE 2019 |
| 1. |
SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement [paper] Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, and Zhiang Wang DAC 2022 |
| 2. |
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling [paper] Liangjian Wen, Yi Zhu, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, and Chunjing Xu ICCAD 2022 |
| 3. |
Floorplanning with Graph Attention [paper] Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang DAC 2022 |
| 4. |
GraphPlanner: Floorplanning with Graph Neural Network [paper] Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, and Li Shang TODAES 2022 |
| 5. |
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs [paper] Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim DAC 2020 |
| 1. |
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning [paper] Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J. -H. Huang, and Evangeline F. Y. Young TCAD 2023 |
| 2. |
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy [paper] Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, and Yibo Lin ASPDAC 2023 |
| 3. |
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning [paper] Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, and Sung Kyu Lim ISPD 2023 |
| 4. |
ChiPFormer: Transferable Chip Placement via Offline Decision Transformer [paper] Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, and Ping Luo ICML 2023 |
| 5. |
AutoDMP: Automated DREAMPlace-based Macro Placement [paper] [code] Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, and Haoxing Ren ISPD 2023 |
| 6. |
Mitigating Distribution Shift for Congestion Optimization in Global Placement [paper] Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, and Martin Wong DAC 2023 |
| 7. |
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction [paper] Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, and Martin Wong ICCAD 2023 |
| 8. |
The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design [paper] Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye HAO, and Junchi Yan NeurIPS 2022 |
| 9. |
MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning [paper] Yao Lai, Yao Mu, and Ping Luo NeurIPS 2022 |
| 10. |
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction [paper] Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, and Pheng Ann Heng DAC 2022 |
| 11. |
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net [paper] Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, and Taewhan Kim ICCAD 2022 |
| 12. |
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions [paper] Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, and Gi-Joon Nam ICCAD 2022 |
| 13. |
Global placement with deep learning-enabled explicit routability optimization [paper] Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, and Bei Yu DATE 2021 |
| 14. |
On Joint Learning for Solving Placement and Routing in Chip Design [paper] Ruoyu Cheng and Junchi Yan NeurIPS 2021 |
| 15. |
Automatic Routability Predictor Development Using Neural Architecture Search [paper] Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chun-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, and Yiran Chen ICCAD 2021 |
| 16. |
PROS: A Plug-in for Routability Optimization Applied in the State-of-the-art Commercial EDA Tool Using Deep Learning [paper] Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, and Evangeline F.Y. Young ICCAD 2021 |
| 17. |
Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction [paper] Amur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, and Mark Coates ICCAD 2021 |
| 18. |
High-Definition Routing Congestion Prediction for Large-Scale FPGAs [paper] Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, and David Z. Pan ASP-DAC 2020 |
| 19. |
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network [paper] Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi Reddy, Shyam Ramji, Gi-Joon Nam, and Jiang Hu ISPD 2020 |
| 20. |
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement [paper] Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, and David Z. Pan DAC 2019 |
| 21. |
Painting on placement: Forecasting routing congestion using conditional generative adversarial nets [paper] Cunxi Yu and Zhiru Zhang DAC 2019 |
| 22. |
Pin accessibility prediction and optimization with deep learning-based pin pattern recognition [paper] Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, and Henry Sheng DAC 2019 |
| 23. |
RouteNet: Routability prediction for mixed-size designs using convolutional neural network [paper] Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, and Jiang Hu ICCAD 2018 |
| 24. |
Routability Optimization for ndustrial Designs at Sub-14nm Process Nodes Using Machine Learning [paper] Wei-Ting J. Chan, Pei-Hsin Ho, Andrew B. Kahng, and Prashant Saxena ISPD 2017 |
| 1. |
BufFormer: A Generative ML Framework for Scalable Buffering [paper] Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, and Haoxing Ren ASPDAC 2023 |
| 2. |
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning [paper] Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim TCAD 2022 |
| 3. |
A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop [paper] Sayed Aresh Beheshti-Shirazi, Ashkan Vakil, Sai Manoj P. D., Ioannis Savidis, Houman Homayoun, and Avesta Sasan GLSVLSI 2021 |
| 4. |
Designing of an Optimization Technique for the Prediction of CTS Outcomes using Neural Network [paper] Shuchi Nagaria and Sujay Deb iSES 2020 |
| 5. |
GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization [paper] Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, and Sung Kyu Lim ICCAD 2019 |
| 1. |
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement [paper] Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, and Martin Wong DAC 2023 |
| 2. |
DPRoute: Deep Learning Framework for Package Routing [paper] Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, and Po-Yang Chen ASPDAC 2023 |
| 3. |
Reinforcement Learning Guided Detailed Routing for FinFET Custom Circuits [paper] Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, and Haoxing Ren ISPD 2023 |
| 4. |
Towards Collaborative Intelligence: Routability Estimation Based on Decentralized Private Data [paper] Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, and Yiran Chen DAC 2022 |
| 5. |
Asynchronous reinforcement learning framework for net order exploration in detailed routing [paper] Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, and Yayi Wei DATE 2021 |
| 6. |
On Joint Learning for Solving Placement and Routing in Chip Design [paper] Ruoyu Cheng and Junchi Yan NeurIPS 2021 |
| 7. |
Late breaking results: A neural network that routes ics [paper] Dmitry Utyamishev and Inna Partin-Vaisband DAC 2020 |
| 1. |
Restructure-Tolerant Timing Prediction via Multimodal Fusion [paper] Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, and Bei Yu DAC 2023 |
| 2. |
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis [paper] Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, and Longxing Shi ASP-DAC 2023 |
| 3. |
Fast and Accurate Wire Timing Estimation Based on Graph Learning [paper] Yuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu, and Longxing Shi DATE 2023 |
| 4. |
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning [paper] Styliani Tompazi, Ioannis Tsiokanos, Jesus Martinez del Rincon, and Georgios Karakonstantis IEEE Des Test 2023 |
| 5. |
Machine-Learning Based Delay Prediction for FPGA Technology Mapping [paper] Hailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, and Ismail Bustany SLIP 2023 |
| 6. |
A timing engine inspired graph neural network model for pre-routing slack prediction [paper] Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z Pan, and Yibo Lin DAC 2022 |
| 7. |
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations [paper] Dongning Ma, Xinqiao Zhang, Ke Huang, Yu Jiang, Wanli Chang, and Xun Jiao TCAD 2022 |
| 8. |
Leveraging Machine Learning for Gate-Level Timing Estimation Using Current Source Models and Effective Capacitance [paper] Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, and George Stamoulis GLSVLSI 2022 |
| 9. |
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis [paper] Ioannis Tsiokanos, Styliani Tompazi, Giorgis Georgakoudis, Lev Mukhanov, and Georgios Karakonstantis TC 2022 |
| 10. |
Generative Self-Supervised Learning for Gate Sizing: Invited [paper] Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren DAC 2022 |
| 11. |
Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation [paper] Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, and Yiran Chen arXiv 2020 |
| 12. |
Routing-free crosstalk prediction [paper] Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, and Gi-Joon Nam ICCAD 2020 |
| 13. |
Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures [paper] Hsien-Han Cheng, Iris Hui-Ru Jiang, and Oscar Ou DAC 2020 |
| 14. |
Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks [paper] Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, and Zhiru Zhang ICCAD 2020 |
| 15. |
TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations [paper] Xun Jiao, Dongning Ma, Wanli Chang, and Yu Jiang DAC 2020 |
| 16. |
DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search [paper] Ioannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, and Georgios Karakonstantis DATE 2020 |
| 17. |
Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism [paper] Erick Carvajal Barboza, Nishchal Shukla, Yiran Chen, and Jiang Hu DAC 2019 |
| 18. |
Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning [paper] Daijoon Hyun, Yuepeng Fan, and Youngsoo Shin DATE 2019 |
| 19. |
Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis [paper] Andrew B. Kahng, Uday Mallappa, and Lawrence Saul ICCD 2018 |
| 20. |
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units [paper] Xun Jiao, Abbas Rahimi, Yu Jiang, Jianguo Wang, Hamed Fatemi, Jose Pineda de Gyvez, and Rajesh K. Gupta TC 2018 |
| 21. |
SI for free: machine learning of interconnect coupling delay and transition effects [paper] Andrew B. Kahng, Mulong Luo, and Siddhartha Nath SLIP 2015 |
| 22. |
A Deep Learning Methodology to Proliferate Golden Signoff Timing [paper] Seung-Soo Han, Andrew B Kahng, Siddhartha Nath, Ashok S Vydyanathan, and ECE Departments DATE 2014 |
| 23. |
Learning-based approximation of interconnect delay and slew in signoff timing tools [paper] Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, and Jyoti Wadhwani SLIP 2013 |
| 1. |
Hotspot Detection via Attention-Based Deep Layout Metric Learning [paper] Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, and Bei Yu TCAD 2022 |
| 2. |
Efficient Hotspot Detection via Graph Neural Network [paper] Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, and Xuan Zeng DATE 2022 |
| 3. |
Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration [paper] Yifeng Xiao, Miaodi Su, Haoyu Yang, Jianli Chen, Jun Yu, and Bei Yu DAC 2021 |
| 4. |
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble [paper] Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, and Xuan Zeng TCAD 2021 |
| 5. |
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning [paper] Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, and Bei Yu TCAD 2021 |
| 6. |
Hotspot Detection via Multi-task Learning and Transformer Encoder [paper] Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, and Martin D.F. Wong ICCAD 2021 |
| 1. |
Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries [paper] Florian Klemme and Hussam Amrouch TCSI 2022 |
| 2. |
Scalable Machine Learning to Estimate the Impact of Aging on Circuits Under Workload Dependency [paper] Florian Klemme and Hussam Amrouch TCSI 2022 |
| 3. |
Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization [paper] Florian Klemme and Hussam Amrouch TCSI 2021 |
| 1. |
Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs [paper] Jincong Lu, Jinwei Zhang, Wentian Jin, Sachin Sachdeva, and Sheldon X. -D. Tan ASPDAC 2023 |
| 2. |
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning [paper] Jianwang Zhai, Yici Cai, and Bei Yu ASPDAC 2023 |
| 1. |
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs [paper] Daijoon Hyun, Younggwang Jung, Insu Cho, and Youngsoo Shin ASP-DAC 2023 |
| 2. |
Vector-Based Dynamic IR-drop Prediction Using Machine Learning [paper] Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chieo-Mo Li, Norman Chang, Ying-Shiun Li, and Wen-Tze Chuang ASP-DAC 2022 |
| 3. |
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification [paper] Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, and Sachin S. Sapatnekar ASP-DAC 2021 |
| 4. |
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks [paper] Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, and Sachin S. Sapatnekar ASP-DAC 2021 |
| 5. |
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance [paper] Xuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, and Cheng-Hong Tsai ICCAD 2020 |
| 6. |
XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network [paper] Chi-Hsien Pao, An-Yu Su, and Yu-Min Lee DATE 2020 |
| 7. |
Fast IR Drop Estimation with Machine Learning [paper] Zhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, and Yiran Chen ICCAD 2020 |
| 8. |
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network [paper] Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, and Yiran Chen ASP-DAC 2020 |
| 9. |
GridNet: Fast Data-Driven EM-induced IR Drop Prediction and Localized Fixing for on-Chip Power Grid Networks [paper] Han Zhou, Wentian Jin, and Sheldon X.-D. Tan ICCAD 2020 |
| 10. |
IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop [paper] Chia-Tung Ho and Andrew B. Kahng ICCAD 2019 |
| 11. |
Machine-Learning-Based Dynamic IR Drop Prediction for ECO [paper] Yen-Chun Fang, Heng-Yi Lin, Min-Yan Sui, Chien-Mo Li, and Eric Jia-Wei Fang ICCAD 2018 |
| 1. |
Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration [paper] Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, and Pheng-Ann Heng ICCAD 2022 |
| 2. |
TransSizer: A Novel Transformer-Based Fast Gate Sizer [paper] Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, and Haoxing Ren ICCAD 2022 |
| 3. |
Rl-sizer: Vlsi gate sizing for timing optimization using deep reinforcement learning [paper] Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim DAC 2021 |
| 4. |
GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning [paper] Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, and Song Han DAC 2020 |
| 1. |
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields [paper] Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, and Martin Wong DAC 2023 |
| 2. |
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography [paper] [code] Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, and Ru Huang ICCAD 2022 |
| 3. |
Generic Lithography Modeling with Dual-Band Optics-Inspired Neural Networks [paper] Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, and Haoxing Ren DAC 2022 |
| 4. |
Robustify ML-Based Lithography Hotspot Detectors [paper] Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, and Yiran Chen ICCAD 2022 |
| 1. |
Enabling Scalable AI Computational Lithography with Physics-Inspired Models [paper] Haoyu Yang and Haoxing Ren ASPDAC 2023 |
| 2. |
Data-Driven Approaches for Process Simulation and Optical Proximity Correction [paper] Hao-Chiang Shao, Chia-Wen Lin, and Shao-Yun Fang ASPDAC 2023 |
| 3. |
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns [paper] Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, and Martin Wong ICCAD 2022 |
| 4. |
DevelSet: Deep Neural Level Set for Instant Mask optimization [paper] Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, and Bei Yu ICCAD 2021 |
| 5. |
DAMO: Deep Agile Mask Optimization for Full Chip Scale [paper] Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, and Bei Yu ICCAD 2020 |
| 6. |
GAN-OPC: Mask Optimization with Lithography-Guided Generative Adversarial Nets [paper] Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, and Evangeline F. Y. Young DAC 2018 |
| 1. |
DiffPattern: Layout Pattern Generation via Discrete Diffusion [paper] Zixiao Wang, Yunheng Shen, Wenqian Zhao, Yang Bai, Guojin Chen, Farzan Farnia, and Bei Yu DAC 2023 |
| 1. |
AnalogCoder: Analog Circuit Design via Training-Free Code Generation [paper] Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z Pan, and Ping Luo arXiv 2024 |
| 2. |
TAG: Learning Circuit Spatial Embedding from Layouts [paper] Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, and Haoxing Ren ICCAD 2022 |
| 3. |
Are Analytical Techniques Worthwhile for Analog IC Placement? [paper] Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, and Jiang Hu DATE 2022 |
| 4. |
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks [paper] Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan DAC 2021 |
| 5. |
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning [paper] Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, and David Z. Pan DATE 2020 |
| 6. |
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout [paper] Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, and David Z. Pan DAC 2019 |
| 1. |
TRouter: Thermal-driven PCB Routing via Non-Local Crisscross Attention Networks [paper] Tinghuan Chen, Silu Xiong, Huan He, and Bei Yu TCAD 2023 |
| 2. |
GeniusRoute: A new analog routing paradigm using generative neural network guidance [paper] Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z Pan ICCAD 2019 |
| 1. |
HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural Network [paper] Wentian Jin, Liang Chen, Subed Lamichhane, Mohammadamir Kavousi, and Sheldon X-D Tan ICCAD 2022 |
| 2. |
A Space-Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing [paper] Tianshu Hou, Ngai Wong, Quan Chen, Zhigang Ji, and Hai-Bao Chen TCAD 2022 |
| 1. |
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line [paper] Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, and Ru Huang DAC 2023 |
| 2. |
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis [paper] [code] [slides] Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, and David Z. Pan DAC 2019 |
| 1. |
A Deep Learning Approach for Efficient Electromagnetic Analysis of On-Chip Inductor with Dummy Metal Fillings [paper] Xiangliang Li, Yijie Tang, Peng Zhao, Shichang Chen, Kuiwen Xu, and Gaofeng Wang Electronics 2022 |
| 2. |
Applications of physics-informed neural networks in power systems-a review [paper] Bin Huang and Jianhui Wang Transactions on Power Systems 2022 |
| 1. |
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction [paper] Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, and Yiran Chen ASPDAC 2023 |
| 2. |
APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning [paper] Ahmet Faruk Budak, David Smart, Brian Swahn, and David Z. Pan ASPDAC 2023 |
| 3. |
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits [paper] Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, and David Z. Pan ASP-DAC 2022 |
| 4. |
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks [paper] Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, and Yibo Lin ASPDAC 2021 |
| 5. |
A Customized Graph Neural Network Model for Guiding Analog IC Placement [paper] Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, and Jiang Hu ICCAD 2020 |
| 1. |
A Thermal Machine Learning Solver For Chip Simulation [paper] Rishikesh Ranade, Haiyang He, Jay Pathak, Norman Chang, Akhilesh Kumar, and Jimin Wen ML4CAD 2022 |
| 2. |
Fast Thermal Analysis for Chiplet Design based on Graph Convolution Networks [paper] Liang Chen, Wentian Jin, and Sheldon X-D Tan ASP-DAC 2022 |
| 1. |
DeepTPI: Test Point Insertion with Deep Reinforcement Learning [paper] Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, and Qiang Xu ITC 2022 |
| 2. |
Neural Fault Analysis for SAT-based ATPG [paper] Junhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, and Yu Huang ITC 2022 |
| 3. |
High Performance Graph Convolutional Networks with Applications in Testability Analysis [paper] Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, and Bei Yu DAC 2019 |
| 1. |
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA) [paper] [code] Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, and Ru Huang SCIENCE CHINA Information Sciences 2022 |
cited as
@article{chen2023ai4eda,
title = {Awesome AI for EDA: A curated paper list of Artificial Intelligence for Electronic Design Automation studies.},
author = {Chen, Guojin and Mai, Jing and Lin, Yibo and Yu, Bei},
journal = {ai4eda.github.io},
year = {2023},
url = {https://ai4eda.github.io/}
}
Last updated on 2024-06-19 .